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Scottsdale, AZ, March 19, 2007

DuPont To Present Technical Papers at 2007 Device Packaging Conference

DuPont Electronic Technologies is pleased to announce that we will once again be participating in the Device Packaging Conference 2007. This year’s event will be held in Scottsdale, AZ on March 19 – 22, 2007. This is an international conference that is organized and sponsored by the International Microelectronics And Packaging Society (IMAPS). The conference provides a focused forum to learn more about the latest technological developments in 5 topics related to microelectronics packaging: FlipChip/CSP; 3D Packaging; Optoelectronics; MEMS; and Biomedical.

At this year’s conference, the DuPont booth (#14-15) will spotlight our thin and thick film offerings for wafer level packaging, WLP photoresist removers from EKC Technology, and Interra™ embedded passive materials. Please plan to stop by the booth to learn more about these products. If that’s not possible, please go to,, or for detailed product information.

In addition to the booth, DuPont is honored to be giving three separate presentations at the conference. Phil Thomas, Global Technology Director, DuPont Electronic Technologies, will be one of the featured speakers at the Global Business Council (GBC). Phil’s presentation, entitled DuPont’s Advanced Materials Pipeline for the Device Packaging Industry, is scheduled for Monday, March 19th at 10:15am.

On Tuesday, March 20th, Dan Amey, Research Fellow, DuPont Electronic Technologies, will present Embedded Capacitor Technology for High Performance Microprocessor Packages. The abstract is listed below:

The integration of embedded Thick Film capacitors and polyimide based planar capacitor materials in IC packages has been investigated in a joint program sponsored by DuPont with the Georgia Institute of Technology Packaging Research Center (PRC). The PRC provided fabrication, electrical modeling and simulation capabilities and DuPont provided the component materials. Test vehicles with different designs were designed, fabricated and tested. The test vehicles included embedded ceramic-fired-on-foil capacitors with microvia interconnects and structures with planar capacitor layers. Measured electrical performance data were used to create models of alternative package designs and to perform simulations to determine the designs offering the most effective power delivery and noise decoupling for a high performance semiconductor package.

The International Roadmap for Semiconductors (ITRS) has projected a substantial increase in the power consumption of microprocessors for future technology nodes. The power delivery network (PDN) provides the power supply to the processor. An improperly designed PDN could be a major source of noise, ground bounce and electromagnetic interference (EMI). A methodology for designing a good PDN is to define a target impedance for the network that should be met over a broad frequency range. The effect of embedded capacitors on PDN noise decoupling and charge supply to the IC versus existing surface mount solutions was studied by fabricating test vehicles with discrete ceramic capacitors and planar polyimide capacitor layers.

To demonstrate the performance of embedded Thick Film fired-on-foil capacitors, test vehicles with different capacitor configurations were designed, fabricated and tested for individual capacitor characterization. The test vehicles included capacitors with microvia interconnects and two sequential build-up layers on each side of a bismaleimide triazine (BT) core. Feature sizes were 12 micron lines and spaces and 50 micron diameter microvias. Other test vehicles used a core layer without build-up layers, planar capacitor layers and arrays of individual embedded capacitors with different size, type and interconnection designs. Each capacitor variation was electrically characterized to select the preferred capacitor design having the best combination of electrical properties and frequency performance. The electrical performance data from the test vehicles was used to create models of alternative package designs and to perform simulations to determine the designs offering the most effective power delivery and noise decoupling.

Due to the low inductance of the embedded ceramic capacitor design there was a significant improvement in power system noise decoupling and charge supply to the IC versus surface mount solutions. The simulations used to compare the performance of the embedded capacitors versus using only surface mount capacitors in semiconductor packages show the capability to provide sufficient capacitance to meet the target impedance needs of Integrated Circuits dissipating 50 to 60 Watts and higher.

A companion program was initiated with the PRC to demonstrate the performance of thin dielectric Planar capacitor power plane layer test vehicles were developed and tested. Reduction of simultaneous switching noise in high speed buses was demonstrated on these active (IC-driven) and passive test vehicles containing 50 ohm single-ended and 100 ohm differential transmission lines, in both stripline and microstrip constructions with via transitions through the thin planar power and ground layers. Based on measured results, simulations of typical micro-processor serial bus configurations were performed showing that thin (1 mil) planar power distribution layers are very effective in reducing simultaneous switching noise, jitter and signal attenuation, especially on single-ended termination, high speed transmission lines.

This paper will describe the test programs and results demonstrating the advantages of low inductance Thick Film embedded capacitor technology and thin planer power distribution layers typical of microprocessor packaging applications.

On Wednesday, March 21st, Pedro Jorge, Global Marketing Manager, DuPont Advanced Packaging Lithography, will present MicroLithographic Polymer Films – A Dry Film Lithography Solution for Advanced Packaging.

This paper describes the development and performance of new dry film based photoresist materials, Microlithographic Polymer Films (MPF) for applications in advanced packaging. An overview of primary applications for thick (100-120 microns) and thin (10-30 microns) MPF is presented, and pro’s and con’s of the new materials are contrasted vs. existing material sets. The performance and process flow for MPF is described for various types of processes on a wafer level. Data is presented from experiments with typical off contact, or soft contact, mask aligners and steppers, as well as newly developed maskless direct imaging processes. Compatibility of MPF with existing and new high productivity metal deposition processes is reported. Finally a cost of ownership model (COO) is presented for MPF, to describe the overall cost of using these new materials both regarding capital investment and processing cost.

For more information on the conference or to register, please go to