DuPont Electronic Technologies will once again participate in the IMAPS Device Packaging Conference 2008. This year’s event will be held at the Radisson Fort McDowell Resort in Scottsdale, Arizona, March 18-20, 2008. The conference provides a focused forum on the latest technological developments related to microelectronics packaging: FlipChip/CSP; 3D Packaging; Optoelectronics; MEMS; and Biomedical.
At this year’s conference, the DuPont booth (#68-69) will spotlight materials and process technologies for WLP and 3D/TSV applications, including our dry film photoresists from Advanced Packaging Lithography, EKC Technology photoresist removers, HD Microsystems redistribution dielectrics and Interra® embedded passive materials. We will also showcase new temporary and permanent adhesive materials for wafer bonding.
DuPont will present five technical papers at the conference.
- Optimization of the Dry Film Lithography Process for Copper Pillar Metallization Applications, is scheduled for March 19th at 7:30 am. » View the Abstract
- A Unique Dry Film Photoresist System for TSV Formation and Protection will be presented on March 19th at 10:30 am. » View the Abstract
- Innovative Photoresist Removal Technology for WLP is also scheduled for March 20th at 10:30 am.
» View the Abstract
- High Performance Photoresist Removers Enable Through Silicon Vias will also be presented on March 19th at 11:30 am, with an exhibit hall poster session.
» View the Abstract
- Photoformable Thick Film Dielectric Process Optimization for Reduced Via Size on March 20th at 10:30 am.
» View the Abstract
For more information on this conference, please visit www.imaps.org/devicepackaging
ABSTRACT—Optimization of the Dry Film Lithography Process for Copper Pillar Metallization Applications
Dry film photoresists have been a critical enabler in Wafer level Packaging since the early 90’s. As wafer diameters have increased from the 200 mm to 300 mm and with discussions underway for potentially 450 mm diameters, the dry film improved thickness uniformity and cost competitiveness versus liquid photoresists will continue to be the key drivers for packaging houses to turn to dry film photoresists. Today, the evolution of semiconductor packaging continues into 3D packaging. Designers and packaging houses are trying to balance the need for more functionality through 3D Packaging while addressing the ROHS concerns. Although solder has been the dominant bump and interconnection choice, increasing ROHS limitations have forced many electronics companies to look for alternative metallic alloys to meet the same functionality demands. To date, copper is becoming the preferred alternative as the interconnect medium. Copper is more environmentally compatible and at the same time reduces the electromigration concerns with solder connections. The other benefit is the easy conversion of the current electroplating tool set from solder to copper chemistries. With a copper electro-deposition process, it is extremely critical for the photoresist to provide sharply defined features that will be metallized. This paper will review the dry film photoresist characterization study performed to optimize the lithography process for copper metallization processes and provide the feature qualities needed for copper plating.
ABSTRACT—A Unique Dry Film Photoresist System for TSV Formation and Protection
Through Silicon Via (TSV) technology has gained a lot of attention lately as a packaging solution meeting the needs for higher device performance and lower cost of ownership. The semiconductor and packaging industry is looking for new technology and alternative materials to meet the goal of true 3D integration. One of the major challenges in implementing 3D packaging is the formation of high aspect ratio interconnects with sufficient via density and uniformity using an efficient process that results in low cost of ownership. This paper demonstrates a novel cost effective dry film photoresist process meeting the technology requirements in terms of via diameter, shape and geometry using resist formulations with high etch selectivity and plating performance for via filling. Further results are presented showing advantages of this photoresist process for TSV “via protection” using the unique tenting capability of dry film.
ABSTRACT—Innovative Photoresist Removal Technology for WLP
A newly developed formulation for thick photo resist removal has been jointly developed by DuPont’s EKC and APL businesses to enable high-performance wafer bumping. This paper describes the compatibility and stripping performance achieved with an innovative photoresist removal technology on various sample wafers with liquid and dry film photo resist. The results presented will open up new opportunities for advanced bumping applications which require pitches of 100µm and below.
ABSTRACT—High Performance Photoresist Removers Enable Through Silicon Vias
The migration of electronic devices to become smaller, lighter, lower cost with more functionality is requiring innovative 3-D packaging approaches. Through silicon vias (TSV) is a packaging method which bonds two or more die together in an integrated structure improving functionality, performance, power consumption, thermal properties and with reduced board real estate. There are two different methods of forming TSV - Via First and Via Last depending on whether the via is made before or after wafer processing. Regardless of the via formation process, an imaging process that enables the formation of high aspect ratio interconnects is a major challenge. New formulations for both dry film materials and photoresist removers have been jointly developed by DuPont’s EKC and APL businesses to enable TSVs for 3D Packaging. This paper describes the compatibility and stripping performance achieved with innovative photoresist removal technology on industry representative TSV wafers.
ABSTRACT—Photoformable Thick Film Dielectric Process Optimization for Reduced Via Size
Integration of an advanced photoformable thick film dielectric composition into a traditional thick film process enables higher density microcircuits. Here we report how 50 micron via openings are achieved using this integrated process with the aid of a novel development tool. In addition, center to center spacing between vias can be reduced beyond the capability of conventional thick film, and used where needed in the integrated multilayer circuit build. The dielectric is compatible with either silver or gold metallurgy thick film conductors. The development tool is designed to readily indicate capability during the process development phase and subsequently serve as a vehicle for process control after the process is transferred into full scale production. This paper describes the photoformable process, materials & properties, development tool, and process optimization experimental results. Recommendations for successful process implementation are given.