IMAPS Advanced Technology Workshop on Integrated/Embedded Passives to Feature Presentations from DuPont
This workshop will feature the latest papers on integrating resistors, capacitors, and inductors into leading edge applications. and will focus on all aspects of passive integration from basic materials to design to manufacturing to applications like SiP. In addition, passive integration technology and market trends will be covered.
Topics will be presented from industry leaders including AVX, DuPont, NXP Semiconductors, Oak Mitsui, Omega Technologies, Samsung and leading research institutions like Georgia Tech, Fraunhofer Institute, IMEC, University of Arkansas and others.
Passive technologies are essential for implementing smaller, cheaper and faster products. This workshop is an opportunity for passive integration developers to interact with industry leaders who are bringing these technologies to the marketplace.
Members of DuPont’s technical staff will chair a session and give two separate presentations at the workshop: Performance Improvements Through the Use of Embedded Capacitors in Flip-Chip IC Packages , scheduled for Thursday, November 15.
On November 16, The Use of Embedded Planar Capacitors for I/O Decoupling will be presented.
For more details, please visit www.imaps.org/passives
Performance Improvements Through the Use of
Embedded Capacitors in Flip-Chip IC Packages
Daniel Amey, Karl Dietz and William Borland
Dupont Electronic Technologies
Research Triangle Park, NC
The integration of embedded Thick Film capacitors and polyimide based planar capacitor laminate materials in IC packages has been investigated by a joint program sponsored by DuPont with the Georgia Institute of Technology Packaging Research Center (PRC). The PRC provided fabrication, electrical modeling and simulation and DuPont provided the component materials. Test vehicles with different designs were fabricated and tested. The test vehicles included embedded ceramic-fired-on-foil Thick Film capacitors with microvia interconnects and structures with planar capacitor laminate layers. Build-up dielectric layers were interconnected by semi-additive processing and laser microvia technology. Measured electrical performance data were used to create models of alternative package designs and to perform simulations to determine the designs offering the most effective power delivery and noise decoupling in accordance with substrate feature needs projected by the ITRS roadmap. The presentation will include integration of capacitors into substrate layers in close proximity to the IC, capacitor interconnections designed for low inductance and low impedance and achieving low target impedance over a mid-frequency range through capacitor designs and arrays resulting in a range of different resonance frequencies.
The Use of Embedded Planar Capacitors for I/O Decoupling
Daniel Amey, Karl Dietz and Sounak Banerji
DuPont Electronic Technologies
Research Triangle Park, NC
Current trends in the electronic industry for increasing miniaturization of electronic products has led to the integration of components within semiconductor packages and boards. Traditionally, discrete decoupling capacitors placed on the surface of the board or the package have been used to decouple active switching circuits. However, with increasing clock rates and their higher harmonics, decoupling has to be provided in the GHz range. Discrete decoupling capacitors are no longer effective in this region because of the increased inductive effects of the current paths of the capacitors. This limits their effectiveness to a maximum of 200 to 400 MHz. Inclusion of embedded planar capacitor laminates in the stackup have shown improvements in the overall power system impedance profile and have been shown to exhibit better noise performance. The main contributor to this superior performance is the reduced inductive effect resulting from conductive planes and thinner dielectric of the embedded laminate.
This presentation discusses the performance of various embedded planar capacitor laminates in decoupling input/output (I/O) circuits. High frequency circuits were designed to demonstrate power system noise reduction and noise coupling suppression between signal traces and power-ground planes. Based on measured results, simulations for different interconnect configurations and thickness’ of embedded planar capacitor laminates were performed The presentation will describe the high frequency passive test vehicles and an active test vehicle designed to compare the simultaneous switching noise improvement of the I/O return current path. Simulations will be presented for high speed single ended and differential buses with data rates of 1Gbps, 5Gbps and 10Gbps. Power system simultaneous switching noise and signal jitter and attenuation (eye diagrams) using embedded capacitor laminates with different constructions and thickness’ will be compared.