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Advanced Semiconductor Packaging & Circuit Materials

Semiconductor Packaging & Circuit Materials



DuPont highlights Wafer Level Packaging Solutions at IMAPS Device Packaging 2009 Conference

DuPont will highlight Wafer Level Packaging Solutions at the IMAPS 5th International Conference and Exhibition on Device Packaging, March 10 - 11, 2009 at Scottsdale, AZ, in booth #55-56. Specifically, DuPont will feature new ultra-low cure dielectric materials for WLP and 3D/TSV applications, and spotlight advanced material sets and process technologies for Fan Out, 3D/TSV, RDL, Bonding and Bumping applications. Two technical papers and two interactive poster sessions will be presented by DuPont at the event:

Technical Papers:

Interactive Poster Sessions:

Please visit us at the show, or contact us to learn more.

Next Generation Photoresist Removal Technology for Wafer Level Packaging To be presented by Anthony Rardin for Cass Shang, DuPont WLP Solutions on Wednesday, March 11 at 8:30 am

A newly developed formulation for thick photo resist removal has been jointly developed by DuPont’s EKC and APL businesses to enable high-performance wafer bumping. This paper describes the compatibility and stripping performance achieved with an innovative photoresist removal technology in various applications with both liquid and dry film photoresists. The results presented will open up new opportunities for advanced bumping applications which require pitches of 100µm and below.

Integrated Materials Enabling TSV/3D To be presented by Anthony Rardin for Toshi Tabashi, DuPont WLP Solutions on Wednesday, March 11 at 9 am

In the long history of IC manufacturing, the industry has been looking to follow “Moore’s law” especially in the FEOL process. From a cost of ownership standpoint, down sizing or increasing density is no longer working. New assembly technologies have been developed to reduce the package size while adding functionality. As a path toward ultimate miniaturization, “System in Package” or MCP technology are good examples for the use of TSV/3D-TSV technology vs. traditional 2D/“in-plane” approaches. This paper examines key process steps used in 3D/TSV technology with regard to critical material properties needed. A portfolio of available materials for the 3D/TSV process is then characterized and evaluated based on recently obtained test data.

Enabling Through Silicon Vias with Compatible Materials To be presented by Pat Starrs, DuPont WLP Solutions during the Interactive Poster Session on Wednesday, March 11 from 1:30 - 2:55 pm

Enabling electronic devices to become smaller and lower cost with more functionality is requiring new innovative 3D packaging approaches.  In 3D/TSV (Through silicon via) two or more die are bonded together and connections are made through the silicon in an integrated structure improving functionality, performance, power consumption, thermal properties and with reduced board real estate. There are two different methods of forming TSV- via first and via last depending on whether the via is made before or after creation of the actual semiconductor device. Regardless of the via formation process, an imaging process that enables the formation of high aspect interconnects is a major challenge. New formulations for dry film, post etch residue removal and photoresist removal have been developed by DuPont Wafer Level Packaging Solutions to enable TSVs for 3-D Packaging. This paper describes the compatibility, residue removal and stripping performance achieved with innovative cleaning technology using industry representative wafers with TSVs created by deep reverse ionic etching (DRIE or “Bosch process”).

Microbump Creation System for 3D Advanced Packaging Applications To be presented by Chester E. Balut, Andy Ahr, DuPont Electronic Technologies; Alan Huffman, RTI International during the Interactive Poster Session on Wednesday, March 11 from 1:30 - 2:55 pm

Today, the electronics market is faced with constant pressure from designers who want to develop “leading edge” products and customers who want more functionality in smaller packages and lower prices. This has driven the need for miniaturized 3D packages to increase portability. With this trend, came increasing I/O density and further shrinkage of the bump pitches. At the same time, the lower processing costs/die of the 300 mm wafers format has driven the need for a photoresist system that not only meets the resolution requirements of the shrinking bump pitches, but is also cost effective. 

The uniform coatability of dry film with minimal waste in the standard wafer bumping applications in the 80 – 100+ micron heights and diameters is a major reason for the industry interest in this alternative to liquid photoresists. Recently, DuPont Wafer Level Packaging Solutions has developed a photoresist/remover chemistry system to address the micro-bump market with a new family of dry films capable of imaging the required less than 50 micron pitch, and cleanly remove them.

The focus of the presentation will be twofold.  The first part will focus on the process development and characterization of the 40 micron thick DuPont MXAdvance * 140 dry film candidate with 2:1 aspect resolution ratio on a 40 micron pitch application with 30 – 40 micron high pillars/micro-bumps. The second part will review the results of the DuPont(tm) EKC162™ remover tests and its impact on copper and lead free, and or solder electro-deposition processes. Together, the combination of a high resolution dry film and effective remover chemistry that strips the photoresist cleanly from the wafers offers customers a viable process for producing micro-bump technologies.