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Semiconductor Fabrication materials from DuPont

Semiconductor Fabrication Materials


Wilmington, DE, May 5, 2008

DuPont will participate in the Symposium on Polymers for Microelectronics

DuPont will participate in the Symposium on Polymers for Microelectronics in Wilmington, DE at the Winterthur Museum on May 7-9, 2008.

DuPont Advanced Packaging Lithography will present two technical papers at the conference.A Unique Dry Film Photoresist System for TSV Formation and Protection on May 8 at 2:45 pm. 
» View the abstract

Optimization of the Dry Film Lithography Process for Copper Pillar Metallization Applications  will be presented during the poster session on May 8 at 6-7:30 pm.
» View the abstract

The Symposium On Polymers for Microelectronics is one of the foremost comprehensive technical meetings for the integration and processing of polyimides and new polymeric films for advanced microelectronic applications. This meeting is sponsored by HD MicroSystems and The Electrochemical Society.

For more information on the Symposium, please visit

Through Silicon Via (TSV) technology has gained a lot of attention lately as a packaging solution meeting the needs for higher device performance and lower cost of ownership. The semiconductor and packaging industry is looking for new technology and alternative materials to meet the goal of true 3D integration. One of the major challenges in implementing 3D packaging is the formation of high aspect ratio interconnects with sufficient via density and uniformity using an efficient process that results in low cost of ownership. This paper demonstrates a novel cost effective dry film photoresist process meeting the technology requirements in terms of via diameter, shape and geometry using resist formulations with high etch selectivity and plating performance for via filling. Further results are presented showing advantages of this photoresist process for TSV “via protection” using the unique tenting capability of dry film.

Dry film photoresists have been a critical enabler in Wafer level Packaging since the early 90’s. As wafer diameters have increased from the 200 mm to 300 mm and with discussions underway for potentially 450 mm diameters, the dry film improved thickness uniformity and cost competitiveness versus liquid photoresists will continue to be the key drivers for packaging houses to turn to dry film photoresists. Today, the evolution of semiconductor packaging continues into 3D packaging. Designers and packaging houses are trying to balance the need for more functionality through 3D Packaging while addressing the ROHS concerns. Although solder has been the dominant bump and interconnection choice, increasing ROHS limitations have forced many electronics companies to look for alternative metallic alloys to meet the same functionality demands. To date, copper is becoming the preferred alternative as the interconnect medium. Copper is more environmentally compatible and at the same time reduces the electromigration concerns with solder connections. The other benefit is the easy conversion of the current electroplating tool set from solder to copper chemistries. With a copper electro-deposition process, it is extremely critical for the photoresist to provide sharply defined features that will be metallized. This paper will review the dry film photoresist characterization study performed to optimize the lithography process for copper metallization processes and provide the feature qualities needed for copper plating.