By: Colin Tsai
DuPont Electronic Technologies, Wafer Level Packaging Solutions
During the last decades, wafer level packaging (WLP) is highlighted as the best next generation CMOS imager sensor package because of strong advantages such as lower cost of ownership (COO), small form factor (3D integration), and better performance.
Nevertheless these benefits, many people are still facing some challenges like micro via creation, low temperature insulation, bottom side oxide etching process, warpage after wafer level bonding with different materials, and the limitation of whole process temperature due to prevention of micro lens damage.
The topic of this study will focus on one DuPont wafer level packaging solutions for CMOS imager sensor with through silicon vias (TSV). As a leading science company in wafer level packaging industry, DuPont electronic technologies offers integrated material and process solutions which can tremendously improve material compatibility in the whole process as well as accelerate customers’ learning curve while developing a new process.
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